The present invention relates to high density integrated circuit devices. In particular, embodiments according to the present invention provide a method for manufacturing and a structure for a conductor connected to multiple planes in a three-dimensional high density device.
Three dimensional (3D) memory devices are characterized by multiple layers, each of which can include a planar array of memory cells. Conductors, that connect to multiple planes, such as a high density word line or bit line structure, can present manufacturing difficulties for 3D memory devices.
In some arrangements, a 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of semiconductor material separated by insulating material. The strips of semiconductor material can include the channels of memory cells in NAND strings, for example. One configuration including these features referred to as a 3D Vertical Gate (3DVG) architecture, is described in U.S. Patent Application Publication No. 2012/0182806 filed 1 Apr. 2011, entitled Memory Architecture Of 3D Array With Alternating Memory String Orientation And String Select Structures, by inventors Shih-Hung Chen and Hang-Ting Lue, which is incorporated by reference as if fully set forth herein.
In a 3DVG architecture, the strips of semiconductor material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductors configured as word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The word lines have surfaces (e.g. bottom surfaces) that conform to the surface of the stacks. This conformal configuration results in a multilayer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines. Memory elements lie in the interface regions between the side surfaces of the strips and the word lines The memory elements are programmable, like the programmable resistance structures or charge trapping structures in the embodiments described below. The combination of the conformal word line, the memory element and the semiconductor strips within a stack at particular interface regions forms a stack of memory cells. As a result of the array structure, a 3D array of memory cells is provided.
In other embodiments, the active strips can be configured as word lines, with vertical bit lines between the strips for vertical NAND string configurations. See for example, commonly owned U.S. Pat. No. 8,363,476, issued 29 Jan. 2013 (filed 19 Jan. 2011), entitled Memory Device, Manufacturing Method And Operating Method Of The Same, by inventors Hang-Ting Lue and Shi-Hung Chen, which is incorporated by reference as if fully set forth herein.
A number of technologies have been pursued to improve the structure of such conductive lines and the processes for making them, as disclosed in our commonly owned U.S. Patent Application Publication No. 2013/0175598 filed on 10 Jan. 2012, entitled Damascene Word Line, by inventors Shih-Hung Chen, Hang-Ting Lue and Yen-Hao Shih; U.S. patent application Ser. No. 13/527,259, filed on 19 Jun. 2012, entitled Damascene Word Line, by inventors Shih-Hung Chen, Yen-Hao Shih and Hang-Ting Lue; U.S. patent application Ser. No. 13/897,702 filed on 20 May 2013, entitled Damascene Conductor for 3D Array, by inventors Ehr-Kun Lai, Yen-Hao Shih and Guanru Lee; and U.S. patent application Ser. No. 13/935,375 filed on 3 Jul. 2013, entitled Damascene Conductor for a 3D Device, by inventors Chia-Jung Chiu and Guanru Lee, which are incorporated by reference as if fully set forth herein.
The formation of conductive lines that include vertical columns between ridges in high aspect ratio trenches, such as those used word lines in the 3DVG architecture, the vertical NAND architecture and other high density structures, can require complex patterning technologies. For example, one approach can require the use of thick hard masks which can withstand the deep etch required to form the vertical columns in the trenches. The use of thick hard masks can make the etch process difficult because they in effect increase the aspect ratio of the trenches. One problem that can result is that strips of conductive residue can be left between the conductive columns in the trenches, which can short out the adjacent conductors.
It is desirable to provide technologies for use as high-density word lines and bit lines of the type that can be used in complex 3D structures, and in other settings requiring conductors that extend into high aspect ratio trenches.